20UPGFC0134218 Chip Configuration

Stage: MODULE/PARYLENE_MASKING

Branch: LP

Config: 6737f63af2d4e487faac9ca3

This Revision: 6737f63af2d4e487faac9ca4

Latest Revision: 6737f63af2d4e487faac9ca4

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA12
SldoTrimD9

Parameter

ADCcalPar
  • -1.0
  • 0.174
  • 10000.0
Name0x20c4a
ChipId14
InjCap7.791
NfDSLDO1.2503837995055413
NfASLDO1.2517979699553212
NfACB1.2491410436557344
VcalPar
  • 14.055
  • 0.186
IrefTrim7
KSenseInA20897.403
KSenseInD21562.015
KSenseShuntA25872.975142857144
KSenseShuntD26695.828095238096
KShuntA1006.82
KShuntD973.185

PixelConfig

Diff from previous revision 67368d4456f39c8f40b1ef46

No diff is present.