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20UPGFC0134220 Chip Configuration

Stage: MODULE/PARYLENE_MASKING

Branch: LP

Config: 6737f632f2d4e487faac9c96

This Revision: 6737f632f2d4e487faac9c97

Latest Revision: 6737f632f2d4e487faac9c97

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	10
SldoTrimD	8

Parameter

ADCcalPar	3.742 0.184 10000.0
Name	0x20c4c
ChipId	13
InjCap	7.927
NfDSLDO	1.2547322211184693
NfASLDO	1.2588604285423155
NfACB	1.254060851745041
VcalPar	13.769 0.198
IrefTrim	7
KSenseInA	20892.375
KSenseInD	21719.532

KSenseShuntA	25866.75
KSenseShuntD	26890.849142857143
KShuntA	1001.001
KShuntD	994.308

PixelConfig

Diff from previous revision 67368d4156f39c8f40b1ef3d

No diff is present.