20UPGFC0096104 Chip Configuration

Stage: MODULE/RECEPTION

Branch: LP

Config: 670e679651efdba6c5f3d68e

This Revision: 670e679751efdba6c5f3d68f

Latest Revision: 670e679751efdba6c5f3d68f

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	12.903 0.179 10000.0
Name	0x17768
ChipId	15
InjCap	7.951
NfDSLDO	1.2861394745250954
NfASLDO	1.284934780941758
NfACB	1.2828552503514734
VcalPar	4.133 0.192
IrefTrim	8
KSenseInA	21073.903
KSenseInD	21511.778

KSenseShuntA	26091.498952380953
KSenseShuntD	26633.629904761903
KShuntA	1048.057
KShuntD	1032.917

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	12.903 0.179 10000.0
Name	0x17768
ChipId	15
InjCap	7.951
NfDSLDO	1.2861394745250954
NfASLDO	1.284934780941758
NfACB	1.2828552503514734
VcalPar	4.133 0.192
IrefTrim	8
KSenseInA	21073.903
KSenseInD	21511.778
KSenseShuntA	26091.498952380953
KSenseShuntD	26633.629904761903
KShuntA	1048.057
KShuntD	1032.917