20UPGFC0096120 Chip Configuration

Stage: MODULE/RECEPTION

Branch: LP

Config: 670e677f51efdba6c5f3d67a

This Revision: None

Latest Revision: 670e678151efdba6c5f3d67b

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	10
SldoTrimD	11

Parameter

ADCcalPar	6.09 0.194 10000.0
Name	0x17778
ChipId	14
InjCap	7.790000000000001
NfDSLDO	1.3038842989123642
NfASLDO	1.2873681728374617
NfACB	1.2853305621488118
VcalPar	3.238 0.207
IrefTrim	9
KSenseInA	21198.778
KSenseInD	21478.88

KSenseShuntA	26246.106095238094
KSenseShuntD	26592.89904761905
KShuntA	1057.893
KShuntD	1053.176

PixelConfig

Diff from previous revision None

No diff is present.