20UPGFC0096072 Chip Configuration

Stage: MODULE/RECEPTION

Branch: LP

Config: 670e676e51efdba6c5f3d666

This Revision: 670e676f51efdba6c5f3d667

Latest Revision: 670e676f51efdba6c5f3d667

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	9.927 0.181 10000.0
Name	0x17748
ChipId	13
InjCap	7.737000000000001
NfDSLDO	1.2862038404184915
NfASLDO	1.2856876554720005
NfACB	1.2841964545154716
VcalPar	3.719 0.194
IrefTrim	6
KSenseInA	21551.804
KSenseInD	21297.455

KSenseShuntA	26683.185904761904
KSenseShuntD	26368.277619047618
KShuntA	1056.644
KShuntD	1020.462

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	9.927 0.181 10000.0
Name	0x17748
ChipId	13
InjCap	7.737000000000001
NfDSLDO	1.2862038404184915
NfASLDO	1.2856876554720005
NfACB	1.2841964545154716
VcalPar	3.719 0.194
IrefTrim	6
KSenseInA	21551.804
KSenseInD	21297.455
KSenseShuntA	26683.185904761904
KSenseShuntD	26368.277619047618
KShuntA	1056.644
KShuntD	1020.462