20UPGFC0096040 Chip Configuration

Stage: MODULE/RECEPTION

Branch: LP

Config: 670e675e51efdba6c5f3d652

This Revision: 670e676051efdba6c5f3d653

Latest Revision: 670e676051efdba6c5f3d653

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	12.797 0.184 10000.0
Name	0x17728
ChipId	12
InjCap	7.94
NfDSLDO	1.288250327012159
NfASLDO	1.2877625055759045
NfACB	1.2853377460839341
VcalPar	4.248 0.199
IrefTrim	11
KSenseInA	21098.55
KSenseInD	21212.031

KSenseShuntA	26122.014285714286
KSenseShuntD	26262.51457142857
KShuntA	1062.04
KShuntD	1034.412

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	12.797 0.184 10000.0
Name	0x17728
ChipId	12
InjCap	7.94
NfDSLDO	1.288250327012159
NfASLDO	1.2877625055759045
NfACB	1.2853377460839341
VcalPar	4.248 0.199
IrefTrim	11
KSenseInA	21098.55
KSenseInD	21212.031
KSenseShuntA	26122.014285714286
KSenseShuntD	26262.51457142857
KShuntA	1062.04
KShuntD	1034.412