20UPGFC0134269 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 670073b16cd1e9c5a1497426

This Revision: 68cb6f1a6d0947a8ea3b7652

Latest Revision: 68cca6186d0947a8ea3b7940

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA8
SldoTrimD9

Parameter

ADCcalPar
  • -1.0
  • 0.184
  • 10000.0
Name0x20c7d
ChipId13
InjCap7.917999999999999
NfDSLDO1.255379206779624
NfASLDO1.256479113462547
NfACB1.2540078945515636
VcalPar
  • 13.137
  • 0.196
IrefTrim6
KSenseInA21003.519
KSenseInD21225.166
KSenseShuntA26004.35685714286
KSenseShuntD26278.77695238095
KShuntA990.031
KShuntD972.629

PixelConfig

Diff from previous revision 681a8e27891fb45189006c98

No diff is present.