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20UPGFC0134233 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6700731a6cd1e9c5a1496602

This Revision: 6716a109af7cafeefcf4f99f

Latest Revision: 67d44e526937b99d1d01a5ee

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	6
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.194 10000.0
Name	0x20c59
ChipId	15
InjCap	7.642
NfDSLDO	1.2512123034054126
NfASLDO	1.2529550185051412
NfACB	1.2500981085055856
VcalPar	13.199 0.206
IrefTrim	12
KSenseInA	21425.693
KSenseInD	21556.228

KSenseShuntA	26527.048476190477
KSenseShuntD	26688.66323809524
KShuntA	1028.11
KShuntD	977.323

PixelConfig

Diff from previous revision 67049697efa50216ebc53d0b

No diff is present.