20UPGFC0134232 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6700731a6cd1e9c5a14965fe

This Revision: 6700731a6cd1e9c5a1496600

Latest Revision: 67049694efa50216ebc53d02

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA8
SldoTrimD8

Parameter

ADCcalPar
  • 5.469
  • 0.187
  • 10000.0
Name0x20c58
ChipId14
InjCap7.681
NfDSLDO1.2517937966833415
NfASLDO1.2531651089114018
NfACB1.2502225014220223
VcalPar
  • 12.823
  • 0.199
IrefTrim7
KSenseInA21023.637
KSenseInD21323.246
KSenseShuntA26029.264857142858
KSenseShuntD26400.209333333332
KShuntA1000.637
KShuntD984.633

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA8
SldoTrimD8
Parameter
ADCcalPar
  • 5.469
  • 0.187
  • 10000.0
Name0x20c58
ChipId14
InjCap7.681
NfDSLDO1.2517937966833415
NfASLDO1.2531651089114018
NfACB1.2502225014220223
VcalPar
  • 12.823
  • 0.199
IrefTrim7
KSenseInA21023.637
KSenseInD21323.246
KSenseShuntA26029.264857142858
KSenseShuntD26400.209333333332
KShuntA1000.637
KShuntD984.633