20UPGFC0134229 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 670072d46cd1e9c5a1496072

This Revision: 67045312255e35fff18274f1

Latest Revision: 6736894556f39c8f40b1e92d

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut23
SerSelOut31
SldoTrimA7
SldoTrimD8

Parameter

ADCcalPar
  • -1.0
  • 0.188
  • 10000.0
Name0x20c55
ChipId14
InjCap7.728
NfDSLDO1.2528038197267068
NfASLDO1.25413227401881
NfACB1.2507182893326534
VcalPar
  • 13.941
  • 0.202
IrefTrim9
KSenseInA21110.863
KSenseInD21965.086
KSenseShuntA26137.25895238095
KSenseShuntD27194.868380952383
KShuntA1005.337
KShuntD1005.271

PixelConfig

Diff from previous revision 670072d46cd1e9c5a1496073

No diff is present.