20UPGFC0134228 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 670072d46cd1e9c5a149606e

This Revision: 6704530e255e35fff18274df

Latest Revision: 6736893f56f39c8f40b1e91b

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA7
SldoTrimD7

Parameter

ADCcalPar
  • 1.577
  • 0.185
  • 10000.0
Name0x20c54
ChipId12
InjCap7.897
NfDSLDO1.2530316983146854
NfASLDO1.2554028624687206
NfACB1.2515890020522906
VcalPar
  • 13.347
  • 0.198
IrefTrim6
KSenseInA21074.359
KSenseInD21639.573
KSenseShuntA26092.063523809524
KSenseShuntD26791.852285714285
KShuntA993.773
KShuntD995.55

PixelConfig

Diff from previous revision 670072d46cd1e9c5a149606f

No diff is present.