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20UPGFC0134200 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 670072806cd1e9c5a1495af7

This Revision: 670072806cd1e9c5a1495af8

Latest Revision: 67368c9e56f39c8f40b1edc6

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	5

Parameter

ADCcalPar	-1.0 0.19 10000.0
Name	0x20c38
ChipId	15
InjCap	7.821
NfDSLDO	1.2509266124054568
NfASLDO	1.2527550348051726
NfACB	1.2496838565556498
VcalPar	12.474 0.205
IrefTrim	11
KSenseInA	21482.516
KSenseInD	21525.791

KSenseShuntA	26597.400761904762
KSenseShuntD	26650.979333333333
KShuntA	1004.715
KShuntD	994.778

PixelConfig

Diff from previous revision None

ITKPIXV2

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SerSelOut0	1
SerSelOut1	3
SerSelOut2	3
SerSelOut3	3
SldoTrimA	9
SldoTrimD	5

Parameter

ADCcalPar	-1.0 0.19 10000.0
Name	0x20c38
ChipId	15
InjCap	7.821
NfDSLDO	1.2509266124054568
NfASLDO	1.2527550348051726
NfACB	1.2496838565556498
VcalPar	12.474 0.205
IrefTrim	11
KSenseInA	21482.516
KSenseInD	21525.791
KSenseShuntA	26597.400761904762
KSenseShuntD	26650.979333333333
KShuntA	1004.715
KShuntD	994.778