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20UPGFC0134203 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 670072806cd1e9c5a1495af5

This Revision: 67368c9b56f39c8f40b1edbe

Latest Revision: 67368c9b56f39c8f40b1edbe

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffLcc	200
DiffLccEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0

EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	15
SerSelOut0	3
SerSelOut1	3
SerSelOut2	3
SerSelOut3	1
SldoTrimA	8
SldoTrimD	10

Parameter

ADCcalPar	-1.0 0.186 10000.0
Name	0x20c3b
ChipId	14
InjCap	7.874
NfDSLDO	1.2534776200761943
NfASLDO	1.2554060471840038
NfACB	1.2522634252305367
VcalPar	14.004 0.199
IrefTrim	9
KSenseInA	21215.078
KSenseInD	21348.274

KSenseShuntA	26266.287047619047
KSenseShuntD	26431.19638095238
KShuntA	1013.825
KShuntD	980.15

PixelConfig

Diff from previous revision 67182d28eb548d6fc10a3b39

No diff is present.