20UPGFC0134242 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 67006f426cd1e9c5a149559b

This Revision: 67042c39255e35fff182732c

Latest Revision: 6736855a56f39c8f40b1e62a

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA5
SldoTrimD6

Parameter

ADCcalPar
  • 2.199
  • 0.187
  • 10000.0
Name0x20c62
ChipId15
InjCap7.868000000000001
NfDSLDO1.2580050638578042
NfASLDO1.2575193972535372
NfACB1.2546482505636076
VcalPar
  • 15.703999999999999
  • 0.202
IrefTrim12
KSenseInA21195.386
KSenseInD21717.83
KSenseShuntA26241.906476190477
KSenseShuntD26888.741904761904
KShuntA998.029
KShuntD993.975

PixelConfig

Diff from previous revision 67007ac66cd1e9c5a1497d27

No diff is present.