20UPGFC0134243 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 67006f426cd1e9c5a1495595

This Revision: 67006f426cd1e9c5a1495596

Latest Revision: 6736855256f39c8f40b1e60f

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD13

Parameter

ADCcalPar
  • 4.152
  • 0.179
  • 10000.0
Name0x20c63
ChipId12
InjCap7.939000000000001
NfDSLDO1.253209712985464
NfASLDO1.2550952484409261
NfACB1.2522098078196882
VcalPar
  • 11.858
  • 0.192
IrefTrim3
KSenseInA21357.993
KSenseInD21472.802
KSenseShuntA26443.229428571427
KSenseShuntD26585.373904761906
KShuntA1013.749
KShuntD983.546

PixelConfig

Diff from previous revision None

ITKPIXV2
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane15
SerSelOut03
SerSelOut13
SerSelOut21
SerSelOut33
SldoTrimA11
SldoTrimD13
Parameter
ADCcalPar
  • 4.152
  • 0.179
  • 10000.0
Name0x20c63
ChipId12
InjCap7.939000000000001
NfDSLDO1.253209712985464
NfASLDO1.2550952484409261
NfACB1.2522098078196882
VcalPar
  • 11.858
  • 0.192
IrefTrim3
KSenseInA21357.993
KSenseInD21472.802
KSenseShuntA26443.229428571427
KSenseShuntD26585.373904761906
KShuntA1013.749
KShuntD983.546