20UPGFC0134221 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66f5fdb4c5fb563270c414df

This Revision: 66ff09d6c57f830c7445fd1e

Latest Revision: 673686b556f39c8f40b1e7cc

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffLcc200
DiffLccEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane15
SerSelOut01
SerSelOut13
SerSelOut23
SerSelOut33
SldoTrimA7
SldoTrimD7

Parameter

ADCcalPar
  • -1.0
  • 0.197
  • 10000.0
Name0x20c4d
ChipId15
InjCap7.899
NfDSLDO1.2584092198474963
NfASLDO1.2603947458195366
NfACB1.256666527987145
VcalPar
  • 12.152
  • 0.21
IrefTrim11
KSenseInA20895.975
KSenseInD21748.19
KSenseShuntA25871.207142857143
KSenseShuntD26926.330476190476
KShuntA1010.342
KShuntD980.305

PixelConfig

Diff from previous revision 66fdc8737b2023e73beeafd6

No diff is present.