20UPGFC0095347 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 66f2d653bc5ccaba629447cc

This Revision: 66f2d655bc5ccaba629447cd

Latest Revision: 66f2d655bc5ccaba629447cd

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA12
SldoTrimD9

Parameter

ADCcalPar
  • 8.2
  • 0.178
  • 10000.0
Name0x17473
ChipId15
InjCap7.861000000000001
NfDSLDO1.287953798131278
NfASLDO1.286833838306816
NfACB1.2845364848207401
VcalPar
  • 3.224
  • 0.191
IrefTrim6
KSenseInA20899.801
KSenseInD21635.057
KSenseShuntA25875.944095238094
KSenseShuntD26786.26104761905
KShuntA1066.512
KShuntD1044.341

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA12
SldoTrimD9
Parameter
ADCcalPar
  • 8.2
  • 0.178
  • 10000.0
Name0x17473
ChipId15
InjCap7.861000000000001
NfDSLDO1.287953798131278
NfASLDO1.286833838306816
NfACB1.2845364848207401
VcalPar
  • 3.224
  • 0.191
IrefTrim6
KSenseInA20899.801
KSenseInD21635.057
KSenseShuntA25875.944095238094
KSenseShuntD26786.26104761905
KShuntA1066.512
KShuntD1044.341