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20UPGFC0095396 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 66f2d649bc5ccaba629447b8

This Revision: 66f2d64abc5ccaba629447b9

Latest Revision: 66f2d64abc5ccaba629447b9

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	10.582 0.186 10000.0
Name	0x174a4
ChipId	14
InjCap	7.813999999999999
NfDSLDO	1.288569943850136
NfASLDO	1.2875078449645956
NfACB	1.2854984686946547
VcalPar	5.321 0.198
IrefTrim	12
KSenseInA	20989.343
KSenseInD	21852.738

KSenseShuntA	25986.80561904762
KSenseShuntD	27055.770857142856
KShuntA	1058.641
KShuntD	1027.457

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	10.582 0.186 10000.0
Name	0x174a4
ChipId	14
InjCap	7.813999999999999
NfDSLDO	1.288569943850136
NfASLDO	1.2875078449645956
NfACB	1.2854984686946547
VcalPar	5.321 0.198
IrefTrim	12
KSenseInA	20989.343
KSenseInD	21852.738
KSenseShuntA	25986.80561904762
KSenseShuntD	27055.770857142856
KShuntA	1058.641
KShuntD	1027.457