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20UPGFC0095394 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 66f2d63bbc5ccaba629447a4

This Revision: 66f2d63cbc5ccaba629447a5

Latest Revision: 66f2d63cbc5ccaba629447a5

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	12.147 0.182 10000.0
Name	0x174a2
ChipId	13
InjCap	7.929999999999999
NfDSLDO	1.291851580729006
NfASLDO	1.2912198614439276
NfACB	1.2884201964305118
VcalPar	5.808 0.196
IrefTrim	10
KSenseInA	21386.304
KSenseInD	21312.663

KSenseShuntA	26478.281142857144
KSenseShuntD	26387.106571428572
KShuntA	1066.618
KShuntD	1041.88

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	12.147 0.182 10000.0
Name	0x174a2
ChipId	13
InjCap	7.929999999999999
NfDSLDO	1.291851580729006
NfASLDO	1.2912198614439276
NfACB	1.2884201964305118
VcalPar	5.808 0.196
IrefTrim	10
KSenseInA	21386.304
KSenseInD	21312.663
KSenseShuntA	26478.281142857144
KSenseShuntD	26387.106571428572
KShuntA	1066.618
KShuntD	1041.88