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20UPGFC0095362 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 66f2d630bc5ccaba62944790

This Revision: 66f2d632bc5ccaba62944791

Latest Revision: 66f2d632bc5ccaba62944791

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	13.657 0.188 10000.0
Name	0x17482
ChipId	12
InjCap	7.795999999999999
NfDSLDO	1.2901824546008673
NfASLDO	1.289450138820468
NfACB	1.2874972967394036
VcalPar	3.709 0.201
IrefTrim	11
KSenseInA	21345.163
KSenseInD	21869.583

KSenseShuntA	26427.344666666668
KSenseShuntD	27076.626571428573
KShuntA	1057.891
KShuntD	1034.693

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	13.657 0.188 10000.0
Name	0x17482
ChipId	12
InjCap	7.795999999999999
NfDSLDO	1.2901824546008673
NfASLDO	1.289450138820468
NfACB	1.2874972967394036
VcalPar	3.709 0.201
IrefTrim	11
KSenseInA	21345.163
KSenseInD	21869.583
KSenseShuntA	26427.344666666668
KSenseShuntD	27076.626571428573
KShuntA	1057.891
KShuntD	1034.693