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20UPGFC0095301 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 66db3742d82248abc217a517

This Revision: 66db3744d82248abc217a519

Latest Revision: 66db3744d82248abc217a519

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	12.657 0.18 10000.0
Name	0x17445
ChipId	15
InjCap	7.800000000000001
NfDSLDO	1.287676495112295
NfASLDO	1.286600382380294
NfACB	1.2847494684812524
VcalPar	4.626 0.195
IrefTrim	8
KSenseInA	21110.049
KSenseInD	21840.606

KSenseShuntA	26136.25114285714
KSenseShuntD	27040.750285714286
KShuntA	1053.923
KShuntD	1042.389

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	8

Parameter

ADCcalPar	12.657 0.18 10000.0
Name	0x17445
ChipId	15
InjCap	7.800000000000001
NfDSLDO	1.287676495112295
NfASLDO	1.286600382380294
NfACB	1.2847494684812524
VcalPar	4.626 0.195
IrefTrim	8
KSenseInA	21110.049
KSenseInD	21840.606
KSenseShuntA	26136.25114285714
KSenseShuntD	27040.750285714286
KShuntA	1053.923
KShuntD	1042.389