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20UPGFC0095317 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 66db3734d82248abc217a4ff

This Revision: 66db3736d82248abc217a500

Latest Revision: 66db3736d82248abc217a500

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	5

Parameter

ADCcalPar	14.928 0.187 10000.0
Name	0x17455
ChipId	14
InjCap	7.6450000000000005
NfDSLDO	1.286946465273162
NfASLDO	1.285238707103648
NfACB	1.2831004216645083
VcalPar	3.053 0.2
IrefTrim	10
KSenseInA	21075.756
KSenseInD	21264.458

KSenseShuntA	26093.793142857143
KSenseShuntD	26327.42419047619
KShuntA	1044.183
KShuntD	1030.274

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	5

Parameter

ADCcalPar	14.928 0.187 10000.0
Name	0x17455
ChipId	14
InjCap	7.6450000000000005
NfDSLDO	1.286946465273162
NfASLDO	1.285238707103648
NfACB	1.2831004216645083
VcalPar	3.053 0.2
IrefTrim	10
KSenseInA	21075.756
KSenseInD	21264.458
KSenseShuntA	26093.793142857143
KSenseShuntD	26327.42419047619
KShuntA	1044.183
KShuntD	1030.274