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20UPGFC0095285 Chip Configuration

Stage: MODULE/FINAL_COLD

Branch: LP

Config: 66db3721d82248abc217a4e7

This Revision: 66db3723d82248abc217a4ec

Latest Revision: 66db3723d82248abc217a4ec

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	12
SldoTrimD	10

Parameter

ADCcalPar	15.678 0.182 10000.0
Name	0x17435
ChipId	13
InjCap	7.786
NfDSLDO	1.2910896476184568
NfASLDO	1.2902855792873298
NfACB	1.2876005653958869
VcalPar	3.589 0.195
IrefTrim	8
KSenseInA	20976.174
KSenseInD	21522.896

KSenseShuntA	25970.50114285714
KSenseShuntD	26647.395047619048
KShuntA	1071.316
KShuntD	1023.664

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	12
SldoTrimD	10

Parameter

ADCcalPar	15.678 0.182 10000.0
Name	0x17435
ChipId	13
InjCap	7.786
NfDSLDO	1.2910896476184568
NfASLDO	1.2902855792873298
NfACB	1.2876005653958869
VcalPar	3.589 0.195
IrefTrim	8
KSenseInA	20976.174
KSenseInD	21522.896
KSenseShuntA	25970.50114285714
KSenseShuntD	26647.395047619048
KShuntA	1071.316
KShuntD	1023.664