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20UPGFC0085314 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66d8f3827641579700e3ff10

This Revision: 66d8f3827641579700e3ff11

Latest Revision: 67d37f03b36e2445a4557a5a

Global Config

AuroraActiveLanes	15
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	-1.0 -1.0 10000.0
Name	0x14d42
ChipId	1
InjCap	-1.0
NfDSLDO	1.2966068514191285
NfASLDO	1.295790258148728
NfACB	1.292967997196641
VcalPar	37.065 0.109
IrefTrim	9
KSenseInA	-1
KSenseInD	14994.055

KSenseShuntA	-1.2380952380952381
KSenseShuntD	18564.068095238094
KShuntA	1071.101
KShuntD	1079.733

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	15
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	15
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	-1.0 -1.0 10000.0
Name	0x14d42
ChipId	1
InjCap	-1.0
NfDSLDO	1.2966068514191285
NfASLDO	1.295790258148728
NfACB	1.292967997196641
VcalPar	37.065 0.109
IrefTrim	9
KSenseInA	-1
KSenseInD	14994.055
KSenseShuntA	-1.2380952380952381
KSenseShuntD	18564.068095238094
KShuntA	1071.101
KShuntD	1079.733