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20UPGFC0088503 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66a2922681cfcd8c814d26fd

This Revision: 66a2922681cfcd8c814d26fe

Latest Revision: 66a2922681cfcd8c814d2702

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	5
CdrClkSel	0

Parameter

ADCcalPar	15.111 0.187 10000.0
Name	0x159b7
ChipId	13
InjCap	7.648
NfDSLDO	1.286066599994957
NfASLDO	1.284875757733396
NfACB	1.2829675406154721
VcalPar	3.278 0.201
IrefTrim	9
KSenseInA	21257.036
KSenseInD	21612.481

KSenseShuntA	26318.235047619048
KSenseShuntD	26758.30980952381
KShuntA	1067.506
KShuntD	1031.93

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	5
CdrClkSel	0

Parameter

ADCcalPar	15.111 0.187 10000.0
Name	0x159b7
ChipId	13
InjCap	7.648
NfDSLDO	1.286066599994957
NfASLDO	1.284875757733396
NfACB	1.2829675406154721
VcalPar	3.278 0.201
IrefTrim	9
KSenseInA	21257.036
KSenseInD	21612.481
KSenseShuntA	26318.235047619048
KSenseShuntD	26758.30980952381
KShuntA	1067.506
KShuntD	1031.93