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20UPGFC0088361 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66a2922581cfcd8c814d26fb

This Revision: 66a2922581cfcd8c814d26fc

Latest Revision: 66a2922681cfcd8c814d2701

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0

DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	8
SldoTrimD	8
CdrClkSel	0

Parameter

ADCcalPar	9.117 0.189 10000.0
Name	0x15929
ChipId	12
InjCap	7.952999999999999
NfDSLDO	1.2891966326892665
NfASLDO	1.2885362497859167
NfACB	1.2863541149748479
VcalPar	3.669 0.201
IrefTrim	9
KSenseInA	21294.409
KSenseInD	21637.643

KSenseShuntA	26364.50638095238
KSenseShuntD	26789.46276190476
KShuntA	1041.445
KShuntD	1054.038

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	8
SldoTrimD	8
CdrClkSel	0

Parameter

ADCcalPar	9.117 0.189 10000.0
Name	0x15929
ChipId	12
InjCap	7.952999999999999
NfDSLDO	1.2891966326892665
NfASLDO	1.2885362497859167
NfACB	1.2863541149748479
VcalPar	3.669 0.201
IrefTrim	9
KSenseInA	21294.409
KSenseInD	21637.643
KSenseShuntA	26364.50638095238
KSenseShuntD	26789.46276190476
KShuntA	1041.445
KShuntD	1054.038