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20UPGFC0088424 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66a2922581cfcd8c814d26f9

This Revision: 66a2922581cfcd8c814d26fa

Latest Revision: 66a2922681cfcd8c814d2700

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	10.343 0.186 10000.0
Name	0x15968
ChipId	15
InjCap	7.780999999999999
NfDSLDO	1.2860254550087753
NfASLDO	1.2853936849172183
NfACB	1.2838429765106696
VcalPar	4.657 0.2
IrefTrim	8
KSenseInA	21284.418
KSenseInD	21335.701

KSenseShuntA	26352.13657142857
KSenseShuntD	26415.62980952381
KShuntA	1060.88
KShuntD	1055.553

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	10.343 0.186 10000.0
Name	0x15968
ChipId	15
InjCap	7.780999999999999
NfDSLDO	1.2860254550087753
NfASLDO	1.2853936849172183
NfACB	1.2838429765106696
VcalPar	4.657 0.2
IrefTrim	8
KSenseInA	21284.418
KSenseInD	21335.701
KSenseShuntA	26352.13657142857
KSenseShuntD	26415.62980952381
KShuntA	1060.88
KShuntD	1055.553