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20UPGFC0088388 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 66a2922581cfcd8c814d26f7

This Revision: 66a2922581cfcd8c814d26f8

Latest Revision: 66a2922681cfcd8c814d26ff

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	13.962 0.188 10000.0
Name	0x15944
ChipId	14
InjCap	8.061
NfDSLDO	1.2910342883382677
NfASLDO	1.2900424345320776
NfACB	1.287814357141361
VcalPar	2.327 0.201
IrefTrim	12
KSenseInA	21161.363
KSenseInD	21750.549

KSenseShuntA	26199.78276190476
KSenseShuntD	26929.25114285714
KShuntA	1076.063
KShuntD	1026.286

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	13.962 0.188 10000.0
Name	0x15944
ChipId	14
InjCap	8.061
NfDSLDO	1.2910342883382677
NfASLDO	1.2900424345320776
NfACB	1.287814357141361
VcalPar	2.327 0.201
IrefTrim	12
KSenseInA	21161.363
KSenseInD	21750.549
KSenseShuntA	26199.78276190476
KSenseShuntD	26929.25114285714
KShuntA	1076.063
KShuntD	1026.286