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20UPGFC0082583 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669c80dfd88a58653436cb5d

This Revision: 669c80dfd88a58653436cb5e

Latest Revision: 66a0233b6cdf72011b6697b2

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0

DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	9.736 0.19 10000.0
Name	0x14297
ChipId	12
InjCap	7.799
NfDSLDO	1.2870007652773006
NfASLDO	1.2857524201641477
NfACB	1.2837435889475801
VcalPar	3.667 0.202
IrefTrim	11
KSenseInA	20891.218
KSenseInD	21480.038

KSenseShuntA	25865.317523809525
KSenseShuntD	26594.332761904763
KShuntA	1060.48
KShuntD	1036.525

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	7
CdrClkSel	0

Parameter

ADCcalPar	9.736 0.19 10000.0
Name	0x14297
ChipId	12
InjCap	7.799
NfDSLDO	1.2870007652773006
NfASLDO	1.2857524201641477
NfACB	1.2837435889475801
VcalPar	3.667 0.202
IrefTrim	11
KSenseInA	20891.218
KSenseInD	21480.038
KSenseShuntA	25865.317523809525
KSenseShuntD	26594.332761904763
KShuntA	1060.48
KShuntD	1036.525