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20UPGFC0090741 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669ab2ac63a7cd79d1ba6ed1

This Revision: 669ab2ac63a7cd79d1ba6ed2

Latest Revision: 669ac1a063a7cd79d1ba7043

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	9

Parameter

ADCcalPar	12.188 0.195 10000.0
Name	0x16275
ChipId	14
InjCap	7.762999999999999
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.769 0.208
IrefTrim	14
KSenseInA	21003.132
KSenseInD	21659.248

KSenseShuntA	26003.877714285714
KSenseShuntD	26816.21180952381
KShuntA	1069.141
KShuntD	1004.547

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	9

Parameter

ADCcalPar	12.188 0.195 10000.0
Name	0x16275
ChipId	14
InjCap	7.762999999999999
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.769 0.208
IrefTrim	14
KSenseInA	21003.132
KSenseInD	21659.248
KSenseShuntA	26003.877714285714
KSenseShuntD	26816.21180952381
KShuntA	1069.141
KShuntD	1004.547