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20UPGFC0090805 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669ab2ac63a7cd79d1ba6ecf

This Revision: 669ab2ac63a7cd79d1ba6ed0

Latest Revision: 669ac19d63a7cd79d1ba703a

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	4
SldoTrimD	2

Parameter

ADCcalPar	7.955 0.196 10000.0
Name	0x162b5
ChipId	13
InjCap	8.016
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.842 0.208
IrefTrim	10
KSenseInA	20938.253
KSenseInD	21142.98

KSenseShuntA	25923.551333333333
KSenseShuntD	26177.022857142856
KShuntA	1152.505
KShuntD	1069.937

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	4
SldoTrimD	2

Parameter

ADCcalPar	7.955 0.196 10000.0
Name	0x162b5
ChipId	13
InjCap	8.016
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.842 0.208
IrefTrim	10
KSenseInA	20938.253
KSenseInD	21142.98
KSenseShuntA	25923.551333333333
KSenseShuntD	26177.022857142856
KShuntA	1152.505
KShuntD	1069.937