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20UPGFC0090773 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669ab2ac63a7cd79d1ba6ecd

This Revision: 669ab2ac63a7cd79d1ba6ece

Latest Revision: 669ac19a63a7cd79d1ba7031

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	3
SldoTrimD	2

Parameter

ADCcalPar	11.739 0.198 10000.0
Name	0x16295
ChipId	12
InjCap	7.729000000000001
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	0.718 0.21
IrefTrim	14
KSenseInA	20885.246
KSenseInD	21324.114

KSenseShuntA	25857.92361904762
KSenseShuntD	26401.284
KShuntA	1120.114
KShuntD	1063.871

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	3
SldoTrimD	2

Parameter

ADCcalPar	11.739 0.198 10000.0
Name	0x16295
ChipId	12
InjCap	7.729000000000001
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	0.718 0.21
IrefTrim	14
KSenseInA	20885.246
KSenseInD	21324.114
KSenseShuntA	25857.92361904762
KSenseShuntD	26401.284
KShuntA	1120.114
KShuntD	1063.871