20UPGFC0090805 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: warm

Config: 669ab2ac63a7cd79d1ba6ebf

This Revision: 669ac08563a7cd79d1ba6fca

Latest Revision: 669adf0fd2b7ecb64abada70

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA4
SldoTrimD2

Parameter

ADCcalPar
  • 7.955
  • 0.196
  • 10000.0
Name0x162b5
ChipId13
InjCap8.016
NfDSLDO-0.015637672243005996
NfASLDO-0.015637672243005996
NfACB-0.015637672243005996
VcalPar
  • -2.0
  • 0.21
IrefTrim10
KSenseInA20938.253
KSenseInD21142.98
KSenseShuntA25923.551333333333
KSenseShuntD26177.022857142856
KShuntA1152.505
KShuntD1069.937

PixelConfig

Diff from previous revision 669abe8b63a7cd79d1ba6f8a

RD53B
Parameter
VcalPar
  • -2.0
  • 0.21