20UPGFC0090722 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669994236798e279bc517684

This Revision: None

Latest Revision: 669994236798e279bc517685

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA4
SldoTrimD9

Parameter

ADCcalPar
  • 9.287
  • 0.196
  • 10000.0
Name0x16262
ChipId15
InjCap7.979
NfDSLDO-0.015637672243005996
NfASLDO-0.015637672243005996
NfACB-0.015637672243005996
VcalPar
  • 1.681
  • 0.209
IrefTrim12
KSenseInA20987.157
KSenseInD21085.619
KSenseShuntA25984.099142857143
KSenseShuntD26106.004476190476
KShuntA1064.206
KShuntD1023.713

PixelConfig

Diff from previous revision None

No diff is present.