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20UPGFC0090694 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669994226798e279bc517682

This Revision: 669994226798e279bc517683

Latest Revision: 669994226798e279bc517683

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	5

Parameter

ADCcalPar	12.585 0.194 10000.0
Name	0x16246
ChipId	14
InjCap	7.797
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.668 0.205
IrefTrim	15
KSenseInA	21184.164
KSenseInD	21472.493

KSenseShuntA	26228.01257142857
KSenseShuntD	26584.99133333333
KShuntA	1003.436
KShuntD	1037.182

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	5

Parameter

ADCcalPar	12.585 0.194 10000.0
Name	0x16246
ChipId	14
InjCap	7.797
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.668 0.205
IrefTrim	15
KSenseInA	21184.164
KSenseInD	21472.493
KSenseShuntA	26228.01257142857
KSenseShuntD	26584.99133333333
KShuntA	1003.436
KShuntD	1037.182