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20UPGFC0090754 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669994226798e279bc517680

This Revision: 669994226798e279bc517681

Latest Revision: 669994226798e279bc517681

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	0
SldoTrimD	0

Parameter

ADCcalPar	-1.0 -1.0 10000.0
Name	0x16282
ChipId	13
InjCap	-1.0
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	0 0
IrefTrim	-1
KSenseInA	21184.164
KSenseInD	21472.493

KSenseShuntA	26228.01257142857
KSenseShuntD	26584.99133333333
KShuntA	-1
KShuntD	-1

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	0
SldoTrimD	0

Parameter

ADCcalPar	-1.0 -1.0 10000.0
Name	0x16282
ChipId	13
InjCap	-1.0
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	0 0
IrefTrim	-1
KSenseInA	21184.164
KSenseInD	21472.493
KSenseShuntA	26228.01257142857
KSenseShuntD	26584.99133333333
KShuntA	-1
KShuntD	-1