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20UPGFC0090709 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 669994226798e279bc51767e

This Revision: 669994226798e279bc51767f

Latest Revision: 669994226798e279bc51767f

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	8

Parameter

ADCcalPar	13.816 0.197 10000.0
Name	0x16255
ChipId	12
InjCap	7.776
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.581 0.211
IrefTrim	13
KSenseInA	20784.205
KSenseInD	21326.575

KSenseShuntA	25732.82523809524
KSenseShuntD	26404.33095238095
KShuntA	1045.08
KShuntD	1032.379

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	7
SldoTrimD	8

Parameter

ADCcalPar	13.816 0.197 10000.0
Name	0x16255
ChipId	12
InjCap	7.776
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	2.581 0.211
IrefTrim	13
KSenseInA	20784.205
KSenseInD	21326.575
KSenseShuntA	25732.82523809524
KSenseShuntD	26404.33095238095
KShuntA	1045.08
KShuntD	1032.379