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20UPGFC0135100 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644de7c078bd48a3ad88f

This Revision: 665644de7c078bd48a3ad890

Latest Revision: 665644de7c078bd48a3ad890

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	6
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.194 10000.0
Name	0x20fbc
ChipId	15
InjCap	8.027
NfDSLDO	1.2529644547570646
NfASLDO	1.2542071774626276
NfACB	1.2518788579108258
VcalPar	14.493 0.209
IrefTrim	15
KSenseInA	21549.169
KSenseInD	21902.745

KSenseShuntA	26679.923523809524
KSenseShuntD	27117.684285714287
KShuntA	995.326
KShuntD	1001.649

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	6
SldoTrimD	7

Parameter

ADCcalPar	-1.0 0.194 10000.0
Name	0x20fbc
ChipId	15
InjCap	8.027
NfDSLDO	1.2529644547570646
NfASLDO	1.2542071774626276
NfACB	1.2518788579108258
VcalPar	14.493 0.209
IrefTrim	15
KSenseInA	21549.169
KSenseInD	21902.745
KSenseShuntA	26679.923523809524
KSenseShuntD	27117.684285714287
KShuntA	995.326
KShuntD	1001.649