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20UPGFC0135081 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644de7c078bd48a3ad88d

This Revision: 665644de7c078bd48a3ad88e

Latest Revision: 665644de7c078bd48a3ad88e

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	3.331 0.187 10000.0
Name	0x20fa9
ChipId	14
InjCap	7.685
NfDSLDO	1.2493035426267152
NfASLDO	1.2503319993682245
NfACB	1.2481608129139274
VcalPar	13.313 0.2
IrefTrim	7
KSenseInA	21508.092
KSenseInD	21884.937

KSenseShuntA	26629.066285714285
KSenseShuntD	27095.636285714285
KShuntA	994.921
KShuntD	1014.261

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	3.331 0.187 10000.0
Name	0x20fa9
ChipId	14
InjCap	7.685
NfDSLDO	1.2493035426267152
NfASLDO	1.2503319993682245
NfACB	1.2481608129139274
VcalPar	13.313 0.2
IrefTrim	7
KSenseInA	21508.092
KSenseInD	21884.937
KSenseShuntA	26629.066285714285
KSenseShuntD	27095.636285714285
KShuntA	994.921
KShuntD	1014.261