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20UPGFC0135094 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644de7c078bd48a3ad88b

This Revision: 665644de7c078bd48a3ad88c

Latest Revision: 665644de7c078bd48a3ad88c

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	3.384 0.186 10000.0
Name	0x20fb6
ChipId	13
InjCap	7.924
NfDSLDO	1.2511253396970397
NfASLDO	1.252753702395127
NfACB	1.250639687664277
VcalPar	12.178 0.198
IrefTrim	9
KSenseInA	21223.724
KSenseInD	21579.482

KSenseShuntA	26276.991619047618
KSenseShuntD	26717.453904761904
KShuntA	1016.155
KShuntD	995.31

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	3.384 0.186 10000.0
Name	0x20fb6
ChipId	13
InjCap	7.924
NfDSLDO	1.2511253396970397
NfASLDO	1.252753702395127
NfACB	1.250639687664277
VcalPar	12.178 0.198
IrefTrim	9
KSenseInA	21223.724
KSenseInD	21579.482
KSenseShuntA	26276.991619047618
KSenseShuntD	26717.453904761904
KShuntA	1016.155
KShuntD	995.31