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20UPGFC0135110 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644de7c078bd48a3ad889

This Revision: 665644de7c078bd48a3ad88a

Latest Revision: 665644de7c078bd48a3ad88a

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	5.538 0.182 10000.0
Name	0x20fc6
ChipId	12
InjCap	8.035
NfDSLDO	1.2508688519868836
NfASLDO	1.2523972631683684
NfACB	1.249926093688024
VcalPar	14.487 0.196
IrefTrim	9
KSenseInA	21127.708
KSenseInD	21735.82

KSenseShuntA	26158.11466666667
KSenseShuntD	26911.01523809524
KShuntA	1005.709
KShuntD	995.63

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	9

Parameter

ADCcalPar	5.538 0.182 10000.0
Name	0x20fc6
ChipId	12
InjCap	8.035
NfDSLDO	1.2508688519868836
NfASLDO	1.2523972631683684
NfACB	1.249926093688024
VcalPar	14.487 0.196
IrefTrim	9
KSenseInA	21127.708
KSenseInD	21735.82
KSenseShuntA	26158.11466666667
KSenseShuntD	26911.01523809524
KShuntA	1005.709
KShuntD	995.63