20UPGFC0135075 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644bf7c078bd48a3ad875

This Revision: 665644bf7c078bd48a3ad876

Latest Revision: 665895ef442c248f1aebb89d

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA9
SldoTrimD7

Parameter

ADCcalPar
  • 3.034
  • 0.19
  • 10000.0
Name0x20fa3
ChipId15
InjCap8.111
NfDSLDO1.2515830628193532
NfASLDO1.2522972736518225
NfACB1.249997514771271
VcalPar
  • 12.333
  • 0.202
IrefTrim10
KSenseInA21361.417
KSenseInD21648.053
KSenseShuntA26447.468666666668
KSenseShuntD26802.351333333332
KShuntA1004.645
KShuntD988.333

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA9
SldoTrimD7
Parameter
ADCcalPar
  • 3.034
  • 0.19
  • 10000.0
Name0x20fa3
ChipId15
InjCap8.111
NfDSLDO1.2515830628193532
NfASLDO1.2522972736518225
NfACB1.249997514771271
VcalPar
  • 12.333
  • 0.202
IrefTrim10
KSenseInA21361.417
KSenseInD21648.053
KSenseShuntA26447.468666666668
KSenseShuntD26802.351333333332
KShuntA1004.645
KShuntD988.333