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20UPGFC0135082 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644bf7c078bd48a3ad873

This Revision: 665644bf7c078bd48a3ad874

Latest Revision: 665895ed442c248f1aebb894

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	11
SldoTrimD	11

Parameter

ADCcalPar	-1.0 0.179 10000.0
Name	0x20faa
ChipId	14
InjCap	7.597000000000001
NfDSLDO	1.249185105205352
NfASLDO	1.2505420922154544
NfACB	1.2485851741061487
VcalPar	14.237 0.193
IrefTrim	10
KSenseInA	21202.512
KSenseInD	21401.553

KSenseShuntA	26250.729142857144
KSenseShuntD	26497.16085714286
KShuntA	1015.739
KShuntD	974.29

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	11
SldoTrimD	11

Parameter

ADCcalPar	-1.0 0.179 10000.0
Name	0x20faa
ChipId	14
InjCap	7.597000000000001
NfDSLDO	1.249185105205352
NfASLDO	1.2505420922154544
NfACB	1.2485851741061487
VcalPar	14.237 0.193
IrefTrim	10
KSenseInA	21202.512
KSenseInD	21401.553
KSenseShuntA	26250.729142857144
KSenseShuntD	26497.16085714286
KShuntA	1015.739
KShuntD	974.29