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20UPGFC0135095 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644bf7c078bd48a3ad871

This Revision: 665644bf7c078bd48a3ad872

Latest Revision: 665895ea442c248f1aebb88b

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	11
SldoTrimD	6

Parameter

ADCcalPar	1.857 0.176 10000.0
Name	0x20fb7
ChipId	13
InjCap	7.699999999999999
NfDSLDO	1.2510926011907595
NfASLDO	1.2525352685963431
NfACB	1.2497927721421642
VcalPar	11.769 0.19
IrefTrim	8
KSenseInA	21633.779
KSenseInD	21492.146

KSenseShuntA	26784.67876190476
KSenseShuntD	26609.32361904762
KShuntA	1000.326
KShuntD	998.322

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	11
SldoTrimD	6

Parameter

ADCcalPar	1.857 0.176 10000.0
Name	0x20fb7
ChipId	13
InjCap	7.699999999999999
NfDSLDO	1.2510926011907595
NfASLDO	1.2525352685963431
NfACB	1.2497927721421642
VcalPar	11.769 0.19
IrefTrim	8
KSenseInA	21633.779
KSenseInD	21492.146
KSenseShuntA	26784.67876190476
KSenseShuntD	26609.32361904762
KShuntA	1000.326
KShuntD	998.322