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20UPGFC0135112 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 665644bf7c078bd48a3ad86f

This Revision: 665644bf7c078bd48a3ad870

Latest Revision: 665895e8442c248f1aebb882

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	8
SldoTrimD	7

Parameter

ADCcalPar	2.227 0.187 10000.0
Name	0x20fc8
ChipId	12
InjCap	7.919999999999999
NfDSLDO	1.2514723249021606
NfASLDO	1.2526007554459921
NfACB	1.2499153764302913
VcalPar	13.037 0.199
IrefTrim	15
KSenseInA	20916.323
KSenseInD	21636.553

KSenseShuntA	25896.399904761904
KSenseShuntD	26788.113238095237
KShuntA	1000.102
KShuntD	972.39

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	8
SldoTrimD	7

Parameter

ADCcalPar	2.227 0.187 10000.0
Name	0x20fc8
ChipId	12
InjCap	7.919999999999999
NfDSLDO	1.2514723249021606
NfASLDO	1.2526007554459921
NfACB	1.2499153764302913
VcalPar	13.037 0.199
IrefTrim	15
KSenseInA	20916.323
KSenseInD	21636.553
KSenseShuntA	25896.399904761904
KSenseShuntD	26788.113238095237
KShuntA	1000.102
KShuntD	972.39