20UPGFC0087226 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: cold

Config: 657ba55c470c358679fbb3ae

This Revision: 657bb2fe470c358679fbb7d5

Latest Revision: 657cc397348fdb8543f62be8

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane8
SldoTrimA8
SldoTrimD5

Parameter

ADCcalPar
  • 10.0
  • 0.192
  • 10000.0
Name0x154ba
ChipId14
InjCap7.19
NfDSLDO1.2865997914556448
NfASLDO1.2847906316480049
NfACB1.2829814718403645
VcalPar
  • 1.0
  • 0.2
IrefTrim10
KSenseInA21047.775
KSenseInD21589.087
KSenseShuntA26059.15
KSenseShuntD26729.34580952381
KShuntA1068.256
KShuntD1033.795

PixelConfig

Diff from previous revision 657bb25d470c358679fbb797

RD53B
Parameter
InjCap7.19