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20UPGFC0087210 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: LP

Config: 657ba54f470c358679fbb3aa

This Revision: 657ba54f470c358679fbb3ab

Latest Revision: 657bb41b470c358679fbb7f6

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	6

Parameter

ADCcalPar	10.252 0.19 10000.0
Name	0x154aa
ChipId	13
InjCap	7.68
NfDSLDO	1.2867066834973793
NfASLDO	1.2855430750908627
NfACB	1.2833307825648927
VcalPar	6.383 0.205
IrefTrim	10
KSenseInA	21323.965
KSenseInD	21836.127

KSenseShuntA	26401.099523809524
KSenseShuntD	27035.204857142857
KShuntA	1052.258
KShuntD	1058.307

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	6

Parameter

ADCcalPar	10.252 0.19 10000.0
Name	0x154aa
ChipId	13
InjCap	7.68
NfDSLDO	1.2867066834973793
NfASLDO	1.2855430750908627
NfACB	1.2833307825648927
VcalPar	6.383 0.205
IrefTrim	10
KSenseInA	21323.965
KSenseInD	21836.127
KSenseShuntA	26401.099523809524
KSenseShuntD	27035.204857142857
KShuntA	1052.258
KShuntD	1058.307