20UPGFC0087210 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: cold

Config: 657ba54e470c358679fbb3a8

This Revision: 657ba75a470c358679fbb3cf

Latest Revision: 657cc395348fdb8543f62bb7

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD6

Parameter

ADCcalPar
  • 8.0
  • 0.192
  • 10000.0
Name0x154aa
ChipId13
InjCap7.68
NfDSLDO1.2867066834973793
NfASLDO1.2855430750908627
NfACB1.2833307825648927
VcalPar
  • 6.383
  • 0.205
IrefTrim10
KSenseInA21323.965
KSenseInD21836.127
KSenseShuntA26401.099523809524
KSenseShuntD27035.204857142857
KShuntA1052.258
KShuntD1058.307

PixelConfig

Diff from previous revision 657ba54f470c358679fbb3a9

RD53B
Parameter
ADCcalPar
$insert
    • 0
    • 8.0
    • 1
    • 0.192
$delete
  • 1
  • 0