20UPGFC0087194 Chip Configuration

Stage: MODULE/POST_PARYLENE_COLD

Branch: cold

Config: 657ba549470c358679fbb3a2

This Revision: 657bb542470c358679fbb85b

Latest Revision: 657cc393348fdb8543f62b86

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane4
SldoTrimA9
SldoTrimD8

Parameter

ADCcalPar
  • 5.0
  • 0.196
  • 10000.0
Name0x1549a
ChipId12
InjCap7.25
NfDSLDO1.2848766554438384
NfASLDO1.283598457016135
NfACB1.2816021695841033
VcalPar
  • 0.0
  • 0.21
IrefTrim10
KSenseInA21072.034
KSenseInD21756.235
KSenseShuntA26089.18495238095
KSenseShuntD26936.290952380954
KShuntA1067.238
KShuntD1068.089

PixelConfig

Diff from previous revision 657bb525470c358679fbb835

No diff is present.