20UPGFC0084917 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: cold

Config: 6573b2d435689ddfe79d041c

This Revision: 6573b2d435689ddfe79d041d

Latest Revision: 6573b2d435689ddfe79d041d

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	4
CdrClkSel	0

Parameter

ADCcalPar	13.149 0.191 10000.0
Name	0x14bb5
ChipId	13
InjCap	7.884000000000001
NfDSLDO	1.2889931350253332
NfASLDO	1.2879041437375998
NfACB	1.2862133414750663
VcalPar	4.454 0.205
IrefTrim	14
KSenseInA	21271.791
KSenseInD	21348.013

KSenseShuntA	26336.503142857142
KSenseShuntD	26430.87323809524
KShuntA	1057.121
KShuntD	1089.833

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	4
CdrClkSel	0

Parameter

ADCcalPar	13.149 0.191 10000.0
Name	0x14bb5
ChipId	13
InjCap	7.884000000000001
NfDSLDO	1.2889931350253332
NfASLDO	1.2879041437375998
NfACB	1.2862133414750663
VcalPar	4.454 0.205
IrefTrim	14
KSenseInA	21271.791
KSenseInD	21348.013
KSenseShuntA	26336.503142857142
KSenseShuntD	26430.87323809524
KShuntA	1057.121
KShuntD	1089.833